1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device including a timing controller with the decreased number of pins.
2. Discussion of the Related Art
In an LCD device with liquid crystal having dielectric anisotropy, an image is displayed by controlling a light transmittance in the liquid crystal. For this, the LCD device includes a liquid crystal display panel with a plurality of pixels arranged in a matrix configuration; and a driving circuit for driving the liquid crystal display panel.
On a display area of the liquid crystal display panel, there are the plurality of pixels defined by gate and data lines crossing each other. Adjacent to a crossing portion of the gate and data lines, there is a thin film transistor (TFT) which is turned-on depending on a scan signal of the gate line to apply a data signal of the data line to each pixel electrode.
The driving circuit includes a gate driver for driving the gate line of the liquid crystal display panel; a data driver for driving the data line; a timing controller for controlling a driving timing in the gate driver and data driver; and a power source for supplying signals needed to drive the liquid crystal display panel and driver.
The gate driver shifts a gate start pulse outputted from the timing controller depending on a gate shift clock, whereby a scan pulse with a gate-on voltage is sequentially supplied to the gate line, and a gate-off voltage is supplied for a period which is not supplied with the scan pulse. In this case, a voltage level of gate shift clock signal outputted from the timing controller is changed by a level shifter, and then the gate shift clock signal with the changed voltage level is supplied to the gate driver.
The gate driver requires the plurality of gate shift clock signals to drive the gate line. Thus, the timing controller has to generate and output the plurality of clock signals. In this respect, the number of output pins in the timing controller is increased. Also, since the plurality of gate shift clock signals are supplied to the gate driver via the level shifter, the number of input pins in the level shifter is increased. For generating the plurality of gate shift clock signals, a circuit structure of the timing controller is complicated, thereby increasing the cost.
FIG. 1 is an exemplary view illustrating a pin connection structure among a timing controller, a level shifter (P-IC), and a liquid crystal display panel in a related art LCD device.
The timing controller generates a start pulse (VST), and a plurality of gate shift clocks (O_GCLK1, 2, 3, 4); and outputs them to the level shifter (P-IC). Also, the timing controller generates switching signals (VDD_E, VDD_O) for an alternate use with TFT so as to reduce a TFT stress of GIP (Gate-In-Panel); and outputs the generated switching signals to the level shifter.
At this time, if VDD_E is high, the first TFT is turned-on and driven; and the second TFT is turned-off. Meanwhile, if VDD_O is high, the first TFT is turned-off; and the second TFT is turned-on and driven.
Meanwhile, the level shifter (Power-IC) receives the VDD_E and VDD_O from the timing controller; and transmits the received VDD_E and VDD_O to the GIP of the liquid crystal display panel.
That is, in case of the GIP of the liquid crystal display panel, the first TFT and second TFT are used while being switched by the two switching signals transmitted from the level shifter. The first TFT and second TFT indicate pull-down transistors in the shift register of the GIP.
In more detail, the GIP outputs the scan signal to each gate line during 1 horizontal period so as to turn-on the switching device (TFT) in each pixel; and outputs a discharging voltage (gate-off voltage) to each gate line during the rest period of 1 frame except the 1 horizontal period so as to turn-off the switching device (TFT). For the output of the discharging voltage, the pull-down transistor in the shift register of the GIP should output the discharging voltage continuously for the rest period of 1 frame except the 1 horizontal period so that the pull-down transistor receives lots of stress. Accordingly, the two pull-down transistors are alternately used so as to prevent the excessive stress.
The related art timing controller transmits the switching signals (VDD_O, VDD_E) enabling to alternately use the two pull-down transistors to the GIP. For this, as shown in FIG. 1, there are additionally-provided two pins for transmitting the switching signal between the timing controller and the level shifter (Power-IC).
As mentioned above, the two pins for transmitting the switching signals should be formed in the related art LCD device, whereby pin and package loss may exist in the timing controller and level shifter.
FIG. 2 is an exemplary view illustrating waveform of signals outputted from the timing controller of the related art LCD device, especially, FIG. 2 illustrates waveform of the two switching signals (VDD_EVEN, VDD_ODD) for controlling the TFT of the GIP liquid crystal display panel.
The related art timing controller and level shifter include the two pins for outputting the VDD_E and VDD_O to thereby switch the two transistors of the GIP. The two pins output the lowest-positioned two waveforms (VDD_EVEN, VDD_ODD) shown in FIG. 2.
That is, as mentioned above, the related art LCD device includes the two pins for transmitting the switching signals via the two lines. Thus, the related art LCD device has the process difficulties and various problems on the arrangement of elements on a PCB.